Tóm tắt

The metal oxide semiconductor capacitors containing Mn doped ZrO2 high-κ films acted as active oxide layerrnwere fabricated on Si (100) wafer by electron beam evaporation. Structural analysis by GIXRD revealed arncomplete tetragonal phase stabilization in ZrO2 thin films when doped with 5 and 8 mol% Mn and annealed atrn500 �C. Film thickness of 40–80 nm was confirmed by XRR and cross-sectional FESEM analysis. Compositionrnanalysis by XPS showed that the ZrO2 thin films were stoichiometric and the Mn ions have existed in þ2rnoxidation state. The film surfaces were obtained to be smooth and crack free when analyzed by FESEM and AFMrnwhere the RMS roughness was found to be in the range from 0.43 to 0.82 nm. All the MOS capacitors have shownrngood capacitance-voltage characteristics with equivalent oxide thicknesses varying from 7.2 to 9.7 nm. Thernhighest dielectric constant of 39.2 was observed in ZrO2 layer with 8 mol% Mn and the dielectric constant wasrnincreasing with Mn concentration. Leakage current in the MOS capacitors was found reduced by an order ofrnmagnitude due to Mn stabilized tetragonal ZrO2 layer. Among the MOS capacitors the leakage current density ofrnas low as 1.28 10 6 A/cm2 was recorded at 1 V with 5 mol% Mn concentration in ZrO2 layer. The complexrnleakage currents across the dielectric layer in the MOS capacitors were explained based on several currentrnconduction mechanisms. Leakage current in these devices was predominantly covered by space charge limitedrnconduction mechanism. At lower voltages (less than 5 V), Poole-Frenkel and Schottky emission were foundrndominant whereas Trap-assisted tunneling and Fowler-Nordheim tunneling had contributed to the leakagerncurrent conduction at voltages greater than 10 V.rn1. IntroductionrnThe urge towards high speed and compact microelectronic gadgets inrnthe present world has created an irresistible demand in the growingrnglobal market. It is apparent from the past four decades that the size ofrndigital electronic devices has been tremendously reduced due to thernemerging miniaturized integrated circuits in silicon processing industry.rnAs predicted by Gordon Moore there is an exponential increase in thernnumber of transistors per chip every year 1. Presently, due to therncontinuous scaling of electronic components in the integrated circuits,rnthickness of the conventionally used SiO2 gate dielectric layer hasrnattained its fundamental limits 2. The oxide thickness has reachedrnbelow 10 nm where a few atomic layers are left, and large vertical gaternleakage currents prevail. Many alternative high-κ materials have beenrnstudied extensively to improve the gate capacitance while maintainingrnthe same physical thickness of the layer equivalent to SiO2 layer and tornreduce the leakage currents. The key requirements for the high-κrnmaterials are that they must possess higher dielectric constant thanrnsilicon dioxide, thermodynamic stability with silicon surface, largernelectronic band offsets which are greater than 1